1. Field of the Invention
The present invention generally relates to a method for manufacturing a semiconductor device, and more specifically, to a technique of forming a domed gate oxide film to relieve stress, which results from different thermal expansive rates between an oxide film and a silicon film during a subsequent thermal process and preventing leakage current between source/drain regions by controlling the thickness of the gate oxide film to improve there fresh characteristics.
2. Description of the Related Art
FIGS. 1a through 1d are cross-sectional diagrams illustrating a method for manufacturing a semiconductor device.
Referring to FIG. 1a, a silicon germanium (hereinafter, referred to as “SiGe”) layer 20 is formed over a semiconductor substrate 10, and grown to form a silicon epitaxial layer 30a. Then, a hard mask layer 40 is formed over the silicon epitaxial layer 30a. 
Thereafter, a photoresist film pattern (not shown) that exposes a gate region is formed, and the hard mask layer 40, the silicon epitaxial layer 30a and the SiGe layer 20 are etched using the photoresist film pattern as an etching mask to expose the semiconductor substrate 10.
Referring to FIG. 1b, after the hard mask layer 40 is removed, the exposed region during the etching process is filled with the silicon epitaxial layer 30b using a Silicon Epitaxial Growth (hereinafter, referred to as “SEG”) method.
Referring to FIG. 1c, the STI process is performed to form a trench, and the SiGe layer 20 is removed with an etchant.
Here, the top of the silicon epitaxial layer 35 is supported by the silicon epitaxial layer 35 at the side of the SiGe layer 20.
Referring to FIG. 1d, a device isolation film (not shown) is formed, and simultaneously a region 25 where the SiGe layer 20 is removed is filled with an oxide film 50.
Next, a deposition layer including a gate polysilicon film 60, a gate metal layer 70 and a gate hard mask layer 80 is formed on the entire surface of the semiconductor substrate 10. The deposition structure is etched to form a gate pattern.
Then, a spacer 90 is formed at a sidewall of the gate pattern to form a gate.
However, the above-described method for manufacturing the semiconductor device is expensive because the formation of the SiGe layer is costly, and has a degraded reliability to manufacture.
Also, an oxide film having a Silicon On Insulator (hereinafter, referred to as “SOI”) structure is formed flat, which causes leakage current between source/drain regions. The oxide film that fills the region where the SiGe layer is removed has a degraded gap-fill characteristics.
Furthermore, contraction and expansion which result from the thermal of the oxide film and silicon film applies stress to the inside of the device, which results in degradation of device characteristics. Although the silicon epitaxial layer at the side of the SiGe layer is required to support the top of the silicon epitaxial layer after the SiGe layer is removed, the silicon epitaxial layer may be collapsed by the stress applied to the semiconductor substrate.